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direct rambus? clock generator w134 ........................ document #: 38 -07426 rev. *c page 1 of 11 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? differential clock source for direct rambus? memory subsystem for up to 800-mhz data transfer rate ? provide synchronization flexibility: the rambus ? channel can optionally be synchronous to an external system or processor clock ? power-managed output allows rambus channel clock to be turned off to mini mize power consumption for mobile applications ? works with cypress cy2210, w133, w158, w159, w161, and w167 to support intel ? architecture platforms ? low-power cmos design packaged in a 24-pin qsop (150-mil ssop) package description the cypress w134m/w134s provides the differential clock signals for a direct rambus me mory subsystem. it includes signals to synchronize the direct rambus channel clock to an external system clock but can al so be used in systems that do not require synchronization of the rambus clock. block diagram pin configuration pll phase pclkm mult0:1 refclk synclkn output logic logic test alignment stopb s0:1 clk clkb s0 s1 vdd gnd clk nc clkb gnd vdd mult0 mult1 gnd 24 23 22 21 20 19 18 17 16 15 14 13 vddir refclk vdd gnd gnd pclkm synclkn gnd vdd vddipd stopb pwrdnb 1 2 3 4 5 6 7 8 9 10 11 12
w134 ............... ......... document #: 38-07426 rev. *c page 2 of 11 pin definitions pin name no. type description refclk 2 i reference clock input . reference clock input, normally supplied by a system frequency synthesizer (cypress w133). pclkm 6 i phase detector input . the phase difference between this signal and synclkn is used to synchronize the rambus channel clock with the system clo ck. both pclkm and synclkn are provided by the gear ratio logic in the memory controller. if gear ratio logic is not used, this pin would be connected to ground. synclkn 7 i phase detector input . the phase difference between this signal and pclkm is used to synchronize the rambus c hannel clock with the system clock. both pclkm and synclkn are provided by the gear ratio logic in the memory controller. if gear ratio logic is not used, this pin would be connected to ground. stopb 11 i clock output enable . when this input is driven to active low, it disables the differential rambus channel clocks. pwrdnb 12 i active low power-down . when this input is driven to active low, it disables the differ- ential rambus channel clocks and places the w134m/w134s in power-down mode. mult 0:1 15, 14 i pll multiplier select . these inputs select the pll prescaler and feedback dividers to determine the multiply ratio for the pll for the input refclk. clk, clkb 20, 18 o complementary output clock . differential rambus channel clock outputs. s0, s1 24, 23 i mode control input . these inputs control the operating mode of the w134m/w134s. nc 19 ? no connect vddir 1 refv reference for refclk . voltage reference for input reference clock. vddipd 10 refv reference for phase detector . voltage reference for phase detector inputs and stopb. vdd 3, 9, 16, 22 p power connection . power supply for core logic and output buffers. connected to 3.3v supply. gnd 4, 5, 8, 13, 17, 21 g ground connection . connect all ground pins to the common system ground plane. mult1 0 1 1 0 mult0 0 0 1 1 w134m pll/refclk 4.5 6 8 5.333 w134s pll/refclk 4 6 8 5.333 s1 0 1 0 1 s0 0 0 1 1 mode normal output enable test bypass te s t w134m/w134s refclk w133 pll phase align d 4 dll rac rmc m n gear ratio logic pclk busclk synclk pclk/m synclk/n w158 w159 w161 w167 figure 1. ddll system architecture cy2210
w134 ............... ......... document #: 38-07426 rev. *c page 3 of 11 key specifications supply voltage:............ ........... ............ ... v dd = 3.3v0.165v operating temperature: ................................... 0c to +70c input threshold:...................................................1.5v typical maximum input voltage: ........................................ v dd +0.5v maximum input frequency: ....... .............. .............. .. 100 mhz output duty cycle:................ ................... 40/60% worst case output type: .......... ............... .. rambus signaling level (rsl) ddll system architecture and gear ratio logic figure 1 shows the distributed delay lock loop (ddll) system architecture, including the main system clock source, the direct rambus clock generato r (drcg), and the core logic that contains the rambus access cell (rac), the rambus memory controller (rmc), and the gear ratio logic. (this diagram abstractly represents the differential clocks as a single busclk wire.) the purpose of the ddll is to frequency-lock and phase-align the core logic and rambus cl ocks (pclk and synclk) at the rmc/rac boundary in order to allow data transfers without incurring additional latency. in the ddll architecture, a pll is used to generate the desired busclk frequency, while a distributed loop forms a dll to align the phase of pclk and synclk at the rmc/rac boundary. the main clock source drives the system clock (pclk) to the core logic, and also drives the reference clock (refclk) to the drcg. for typical intel architecture platforms, refclk will be half the cpu front side bus frequency. a pll inside the drcg multiplies refclk to generate the desired frequency for busclk, and busclk is driven through a terminated transmission line (rambus channel). at the mid- point of the channel, the rac senses busclk using its own dll for clock alignment, followed by a fixed divide-by-4 that generates synclk. pclk is the clock used in the memory controller (rmc) in the core logic, and synclk is the clock used at the core logic interface of the rac. the ddll together with the gear ratio logic enables users to exchange data directly from the pclk domain to the synclk domain without incurring additional latency for synchronization. in general, pclk and synclk can be of different frequencies, so the gear ratio logic must select the appropriate m and n dividers such that the frequencies of pclk/m and synclk/n are equal. in one inter- esting example, pclk = 133 mhz, synclk = 100 mhz, and m = 4 while n = 3, giving pclk/m = synclk/n = 33 mhz. this example of the clock waveforms with the gear ratio logic is shown in figure 2 . the output clocks from the gear ratio logic, pclk/m, and synclk/n, are output from the core logic and routed to the drcg phase detector inputs. the routing of pclk/m and synclk/n must be matched in the core logic as well as on the board. after comparing the phase of pclk/m vs. synclk/n, the drcg phase detector drives a phase al igner that adjusts the phase of the drcg output clock, busclk. since everything else in the distributed loop is fixed delay, adjusting busclk adjusts the phase of synclk and thus the phase of synclk/n. in this manner the distributed loop adjusts the phase of synclk/n to match that of pclk/m, nulling the phase error at the input of the drcg phase detector. when the clocks are aligned, data can be exchanged directly from t he pclk domain to the synclk domain. table 1 shows the combinations of pclk and busclk frequencies of greatest interest, organized by gear ratio. pclk synclk pclk/m = synclk/n figure 2. gear ratio timing diagram table 1. supported pclk and buscl k frequencies, by gear ratio pclk gear ratio and busclk 2.0 1.5 1.33 1.0 67 mhz 267 mhz 100 mhz 300 mhz 400 mhz 133 mhz 267 mhz 356 mhz 400 mhz 150 mhz 400 mhz 200 mhz 400 mhz
w134 ............... ......... document #: 38-07426 rev. *c page 4 of 11 figure 3 shows more details of th e ddll system architecture, including the drcg output enable and bypass modes. phase detector signals the drcg phase detector receives two inputs from the core logic, pclkm (pclk/m) and synclkn (synclk/n). the m and n dividers in the core logic are chosen so that the frequencies of pclkm and synclkn are identical . the phase detector detects the phase difference between the two input clocks, and drives the drcg phase aligner to null the input phase error through the distributed loop. when the loop is locked, the input phase error between pclkm and synclkn is within the specification t err,pd given in the device charac teristics table after the lock time given in the state transition section. the phase detector aligns the rising edge of pclkm to the rising edge of sync lkn. the duty cycle of the phase detector input clocks will be within the specification dc in,pd given in the operating conditions table. beca use the duty cycles of the two phase detector input clocks w ill not necessarily be identical, the falling edges of pclkm and synclkn may not be aligned when the rising edges are aligned. the voltage levels of the pclk m and synclkn signals are deter- mined by the controller. the pin vddipd is used as the voltage reference for the phase detector inputs and should be connected to the output voltage supply of the controller. in some applications, the drcg pll output clock will be used directly, by bypassing the phase aligner. if pclkm and synclkn are not used, those inputs must be grounded. selection logic ta ble 2 shows the logic for selecting the pll prescaler and feedback dividers to determine the multiply ratio for the pll from the input refclk. divider a sets the feedback and divider b sets the prescaler, so the pll output clock frequency is set by: pllclk = refclk*a/b. table 3 shows the logic for enabling the clock outputs, using the stopb input signal. when stopb is high, the drcg is in its normal mode, and clk and clkb are complementary outputs following the phase aligner output (paclk). when stopb is low, the drcg is in the clk stop mode, the output clock drivers are disabled (set to hi-z), and the clk and clkb settle to the dc voltage v x,stop as given in the device character- istics table. the level of v x,stop is set by an external resistor network. table 4 shows the logic for sele cting the bypass and test modes. the select bits, s0 and s1, control the selection of these modes. the bypass mode br ings out the full-speed pll output clock, bypassing the phase aligner. the test mode brings the refclk input all the way to the output, bypassing both the pll and the phase aligner. in the output test mode (oe), both the clk and clkb outputs are put into a high-impedance state (hi-z). this can be used for component testing and for board-level testing. w134m/w134s refclk w133 pll phase align d 4 dll rac rmc m n gear ratio logic pclk busclk synclk pclk/m synclk/n s0/s1 stopb w158 w159 w161 w167 figure 3. ddll including details of drcg cy2210 table 2. pll divider selection mult0 mult1 w134m w134s abab 009241 016161 118181 10163163 table 3. clock stop mode selection mode stopb clk clkb normal 1 paclk paclkb clk stop 0 v x,stop v x,stop
w134 ............... ......... document #: 38-07426 rev. *c page 5 of 11 ta ble 5 shows the logic for selecting the power-down mode, using the pwrdnb input signal. pwrdnb is active low (enabled when 0). when pwrdnb is disabled, the drcg is in its normal mode. when pwrdnb is enabled, the drcg is put into a powered-off state, and the clk and clkb outputs are three-stated. table of frequencies and gear ratios ta ble 6 shows several suppor ted pclk and busclk frequencies, the corresponding a and b dividers required in the drcg pll, and the corresponding m and n dividers in the gear ratio logic. the column ratio gives the gear ratio as defined pclk/synclk (same as m and n). the column f@pd gives the divided down frequency (in mhz) at the phase detector, where f@pd = pclk/m = synclk/n. state transitions the clock source has three fundamental operating states. figure 4 shows the state diagram with each transition labelled a through h. note that the clock source output may not be glitch-free during state transitions. upon powering up the device, the device can enter any state, depending on the settings of the control signals, pwrdnb and stopb. in power-down mode, the clock source is powered down with the control signal, pwrdnb, equal to 0. the control signals s0 and s1 must be stable before power is applied to the device, and can only be changed in power-down mode (pwrdnb = 0). the reference inputs, v ddr and v ddpd , may remain on or may be grounded during the power-down mode. the control signals mult0 and mult1 can be used in two ways. if they are changed during power-down mode, then the power-down transition timings determine the settling time of the drcg. however, the mult0 and mult1 control signals can also be changed during normal mode. when the mult control signals are ?hot-swapped? in th is manner, the mult transition timings determine the settling time of the drcg. in normal mode, the clock source is on, and the output is enabled. table 7 lists the control signals for each state. figure 5 shows the timing diagrams for the various transitions between states, and table 8 specifies the latencies of each state transition. note that these transition latencies assume the following. refclk input has settled and me ets specification shown in the operating conditions table. the mult0, mult1, s0 and s1 control signals are stable. table 4. bypass and test mode selection mode s0 s1 bypclk (int.) clk clkb normal 0 0 gnd paclk paclkb output test (oe) 0 1 ? hi-z hi-z bypass 1 0 pllclk pllclk pllclkb test 1 1 refclk refclk refclkb table 5. power-down mode selection mode pwrdnb clk clkb normal 1 paclk paclkb power-down 0 gnd gnd table 6. examples of frequencies, dividers, and gear ratios pclk refclk busclk synclk a b m n ratio f@pd 67 33 267 67 8 1 2 2 1.0 33 100 50 300 75 6 1 8 6 1.33 12.5 100 50 400 100 8 1 4 4 1.0 25 133 67 267 67 4 1 4 2 2.0 33 133 67 400 100 6 1 8 6 1.33 16.7 table 7. control signals for clock source states state pwrdnb stopb clock source output buffer power-down 0 x off ground clock stop 1 0 on disabled normal 1 1 on enabled test m n l k normal power-down clk stop d c g a e f h vdd turn-on vdd turn-on vdd turn-on vdd turn-on b j figure 4. clock source state diagram
w134 ............... ......... document #: 38-07426 rev. *c page 6 of 11 timing diagrams table 8. state transition latency specifications transition from to transition latency description parameter max. a power-down normal t powerup 3 ms time from pwrdnb to clk/clkb output settled (excluding t distlock ). c power-down clk stop t powerup 3 ms time from pwrdnb until the internal pll and clock has turned on and settled. k power-down test t powerup 3 ms time from pwrdnb to clk/clkb output settled (excluding t distlock ). gv dd on normal t powerup 3 ms time from v dd is applied and settled until clk/clkb output settled (excluding t distlock ). hv dd on clk stop t powerup 3 ms time from v dd is applied and settled until internal pll and clock has turned on and settled. mv dd on test t powerup 3 ms time from v dd is applied and settled until internal pll and clock has turned on and settled. j normal normal t mult 1 ms time from when mult0 or mult1 changed until clk/clkb output resettled (excluding t distlock ). t powerup t powerdn t stop t on t clkon t clkoff t clksetl pwrdnb clk/clkb power-down exit and entry output enable control stopb clk/clkb output clock not specified glitches may clock enabled and glitch-free clock output settled within 50 ps of the phase before disabled occur figure 5. state transition timing diagrams t mult clk/clkb mult0 and/or mult1 figure 6. multiply transition timing
w134 ............... ......... document #: 38-07426 rev. *c page 7 of 11 figure 5 shows that the clk stop to normal transition goes through three phases. during t clkon , the clock output is not specified and can have glitches. for t clkon < t < t clksetl , the clock output is enabled and must be glitch-free. for t>t clksetl , the clock output phase must be settled to within 50 ps of the phase before the clock output was disabled. at this time, the clock output must also meet the voltage and timing specifications of the devi ce characteristics table. the outputs are in a high-impedance state during the clk stop mode. e clk stop normal t clkon 10 ns time from stopb until clk/clkb provides glitch-free clock edges. e clk stop normal t clksetl 20 cycles time from stopb to clk/ clkb output settle d to within 50 ps of the phase before clk/clkb was disabled. f normal clk stop t clkoff 5 ns time from stopb to clk/clkb output disabled. ltestnormalt ctl 3 ms time from when s0 or s1 is changed until clk/clkb output has resettled (excluding t distlock ). n normal test t ctl 3 ms time from when s0 or s1 is changed until clk/clkb output has resettled (excluding t distlock ). b,d normal or clk stop power-down t powerdn 1 ms time from pwrdnb to the device in power-down. table 8. state transition latency specifications (continued) transition from to transition latency description parameter max. table 9. distributed loop lock time specification parameter descrip tion min. max. unit t distlock time from when clk/clkb output is settled to when the phase error between synclkn and pclkm falls within the t err,pd spec in table . 5ms table 10.supply and reference current specification parameter description min. max. unit i powerdown ?supply? current in power-down state (pwrdnb 1 = 0) ? 250 a i clkstop ?supply? current in clk stop state (stopb = 0) ? 65 ma i normal ?supply? current in normal state (stopb = 1, pwrdnb = 1) ? 100 ma i ref,pwdn current at vddir or vddipd reference pin in power-down state (pwrdnb = 0) ? 50 a i ref,norm current at vddir or vddipd reference pin in normal or clk stop state (pwrdnb = 1) ? 2 ma
w134 ............... ......... document #: 38-07426 rev. *c page 8 of 11 notes: 1. represents stress ratings only, and functional operation at the maximums is not guaranteed. 2. gives the nominal values of the external component s and their maximum acceptable tolerance, assuming z ch = 28 ? . 3. do not populate c f . leave pads for future use. 4. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 5. refclk jitter measured at v ddir (nom)/2. 6. if input modulation is used: input modulation is allowed but not required. 7. capacitance measured at freq=1 mhz, dc bias = 0.9v and v ac < 100 mv. 8. the amount of allowed spreading for any non-triangular modul ation is determined by the induced downstream tracking skew, whic h cannot exceed the skew generated by the specified 0.6% triangular modulation. typica lly, the amount of allowed non-triangular modulation is about 0.5% . absolute maximum conditions [1] parameter description min. max. unit v dd, abs max. voltage on v dd with respect to ground ?0.5 4.0 v v i, abs max. voltage on any pin with respect ground ?0.5 v dd + 0.5 v external component values [2] parameter description min. max. unit r s serial resistor 39 5% ? r p parallel resistor 51 5% ? c f edge rate filter capacitor 4?15 [3] 10% pf c mid ac ground capacitor 470 pf 0.1 ? f20% operating conditions [4] parameter description min. max. unit v dd supply voltage 3.135 3.465 v t a ambient operating temperature 0 70 c t cycle,in refclk input cycle time 10 40 ns t j,in input cycle-to-cycle jitter [5] ? 250 ps dc in input duty cycle over 10,000 cycles 40 60 %t cycle fm in input frequency of modulation 30 33 khz pm in [6] modulation index for triangular modulation ? 0.6 % modulation index for non-triangular modulation ? 0.5 [8] % t cycle,pd phase detector input cycle time at pclkm & synclkn 30 100 ns t err,init initial phase error at phase detector inputs ?0.5 0.5 t cycle,pd dc in,pd phase detector input duty cycle over 10,000 cycles 25 75 t cycle,pd t i,sr input slew rate (measured at 20%-80% of input voltage) for pclkm, synclkn, and refclk 14v/ns c in,pd input capacitance at pclkm, synclkn, and refclk [7] ?7pf dc in,pd input capacitance matching at pclkm and synclkn [7] ?0.5pf c in,cmos input capacitance at cmos pins (excluding pclkm, synclkn, and refclk) [7] ?10pf v il input (cmos) signal low voltage ? 0.3 vdd v ih input (cmos) signal high voltage 0.7 ? vdd v il,r refclk input low voltage ? 0.3 v ddir v ih,r refclk input high voltage 0.7 ? v ddir v il,pd input signal low voltage for pd inputs and stopb ? 0.3 v ddipd v ih,pd input signal high voltage for pd inputs and stopb 0.7 ? v ddipd v ddir input supply reference for refclk 1.235 3.465 v v ddipd input supply reference for pd inputs 1.235 2.625 v
w134 ............... ......... document #: 38-07426 rev. *c page 9 of 11 notes: 9. output jitter spec measured at t cycle = 2.5 ns. 10. output jitter spec measured at t cycle = 3.75 ns. 11. v cos = v oh ?v ol. 12. r out = dv o / d i o . this is defined at the output pins. device characteristics parameter description min. max. unit t cycle clock cycle time 2.5 3.75 ns t j cycle-to-cycle jitter at clk/clkb [9] ?60ps total jitter over 2, 3, or 4 clock cycles [9] ? 100 ps 266-mhz cycle-to-cycle jitter [10] ? 100 ps 266-mhz total jitter over 2, 3, or 4 clock cycles [10] ? 160 ps t step phase aligner phase step size (at clk/clkb) 1 ? ps t err,pd phase detector phase error fo r distributed loop measured at pclkm-synclkn (rising edges) ( does not include clock jitter) ?100 100 ps t err,ssc pll output phase error when tracking ssc ?100 100 ps v x,stop output voltage during clk stop (stopb=0) 1.1 2.0 v v x differential output crossing-point voltage 1.3 1.8 v v cos output voltage swing (p-p single-ended) [11] 0.4 0.6 v v oh output high voltage ? 2.0 v v ol output low voltage 1.0 ? v r out output dynamic resistance (at pins) [12] 12 50 ? i oz output current during hi-z (s0 = 0, s1 = 1) ? 50 ? a i oz,stop output current during clk stop (stopb = 0) ? 500 ? a dc output duty cycle over 10,000 cycles 40 60 %t cycle t dc,err output cycle-to-cycle duty cycle error ? 50 ps t r, t f output rise and fall times (measured at 20%?80% of output voltage) 250 500 ps t cr,cf difference between output rise and fall times on the same pin of a single device (20%?80%) ? 100 ps
w134 ............... ....... document #: 38-07426 rev. *c page 10 of 11 layout example 21 20 19 18 17 15 14 13 6 7 1 2 4 5 g vddir g vddipd 24 23 22 g 3 8 9 11 12 10 g g internal power supply plane 46 g g fb +3.3v supply c4 10 ? f 0.005 ? f g g c3 g g g g g g g g g g g g = via to gnd plane layer fb = dale ilb1206 - 300 (300 ?? @ 100 mhz) all bypass cap = 0.1 ceramic xr7 ordering information ordering code package type W134H 24-pin qsop (150 mils, ssop) W134Ht 24-pin qsop (150 mils, ssop) ? tape and reel w134sh 24-pin qsop (150 mils, ssop) w134sht 24-pin qsop (150 mils, ssop) ? tape and reel lead-free cyw134moxc 24-pin qsop (150 mils, ssop) cyw134moxct 24-pin qsop (150 mils, ssop), tape and reel cyw134soxc 24-pin qsop (150 mils, ssop) cyw134soxct 24-pin qsop (150 mils, ssop), tape and reel
w134 ...................... document #: 38 -07426 rev. *c page 11 of 11 the information in this document is believed to be accurate in all respects at the time of p ublication but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibil ity for any consequences resulti ng from the use of information included herein. additi onally, silicon laboratories assumes no res ponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon labor atories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other a pplication in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. package diagram 24-lead quarter size outline q13

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